• Your shopping cart is empty!

  • JEDEC JESD60A
Provide PDF Format

Learn More

JEDEC JESD60A

  • A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS
  • standard by JEDEC Solid State Technology Association, 09/01/2004
  • Publisher: JEDEC

$34.00$67.00


This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process.

Product Details

Published:
09/01/2004
Number of Pages:
24
File Size:
1 file , 85 KB

Related Products

JEDEC JESD 212

JEDEC JESD 212

GDDR5 SGRAM..

$96.00 $191.00

JEDEC JESD22-A100C

JEDEC JESD22-A100C

CYCLED TEMPERATURE HUMIDITY BIAS LIFE TEST..

$27.00 $53.00

JEDEC JESD70

JEDEC JESD70

2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS..

$27.00 $53.00

JEDEC JESD241

JEDEC JESD241

Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities..

$37.00 $74.00