Provide PDF Format
JEDEC JESD241
- Procedure for Wafer-Level DC Characterization of Bias Temperature Instabilities
- standard by JEDEC Solid State Technology Association, 12/01/2015
- Publisher: JEDEC
$37.00$74.00
This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document.
Related Products
JEDEC JESD76-1
STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION)..
$24.00 $48.00
JEDEC J-STD-609A.01
AND LABELING OF COMPONENTS, PCBs AND PCBAs TO IDENTIFY LEAD (Pb), Pb-FREE AND OTHER ATTRIBUTES..
$30.00 $59.00
JEDEC JESD 46C
CUSTOMER NOTIFICATION OF PRODUCT/PROCESS CHANGES BY SEMICONDUCTOR SUPPLIERS..
$27.00 $53.00
JEDEC JESD 22-A121A (R2014)
MEASURING WHISKER GROWTH ON TIN AND TIN ALLOY SURFACE FINISHES..
$37.00 $74.00