• JEDEC JESD202
Provide PDF Format

Learn More

JEDEC JESD202

  • METHOD FOR CHARACTERIZING THE ELECTROMIGRATION FAILURE TIME DISTRIBUTION OF INTERCONNECTS UNDER CONSTANT-CURRENT AND TEMPERATURE STRESS
  • standard by JEDEC Solid State Technology Association, 03/01/2006
  • Publisher: JEDEC

$31.00$61.00


This is an accelerated stress test method for determining sample estimates and their confidence limits of the median-time-to-failure, sigma, and early percentile of a log-Normal distribution, which are used to characterize the electromigration failure-time distribution of equivalent metal lines subjected to a constant current-density and temperature stress. Failure is defined as some pre-selected fractional increase in the resistance of the line under test. Analysis procedures are provided to analyze complete and singly, right-censored failure-time data. Sample calculations for complete and right-censored data are provided in Annex A. The analyses are not intended for the case when the failure distribution cannot be characterized by a single log-Normal distribution.

Related Products

JEDEC JESD7-A

JEDEC JESD7-A

STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES..

$71.00 $141.00

JEDEC JESD71

JEDEC JESD71

STANDARD TEST AND PROGRAMMING LANGUAGE (STAPL)..

$44.00 $87.00

JEDEC JESD84-B50

JEDEC JESD84-B50

Embedded Multi-media card (e*MMC), Electrical Standard 5.0..

$153.00 $305.00

JEDEC JESD220A

JEDEC JESD220A

Universal Flash Storage (UFS)..

$178.00 $355.00