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JEDEC JESD 82-24
- DEFINITION OF the SSTUB32865 28-bit 1:2 REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS
- standard by JEDEC Solid State Technology Association, 05/01/2007
- Publisher: JEDEC
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This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410MHz.
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